In many computer systems, circuits utilize static logic CMOS (Complimentary Metal Oxide Semiconductor), where the signals of interest are single-ended signals. To increase speed and noise immunity, it may be desirable for high performance computer systems to employ current-mode logic circuits utilizing differential signaling. For example, in the simplified system of FIG. 1, die 102 and die 104 may communicate to each other via die 106, where die 102 and 104 may each comprise a microprocessor and die 106 comprises a switch. Switch 106 may also allow communication with cache 108, which is not on the same die as switch 106 or microprocessors 102 and 104. For speed and noise immunity, some or all of the signaling used for communication in the system of FIG. 1 may include differential signaling with current-mode transmission circuits, but many of the circuits in the microprocessors and switch may employ static logic CMOS. Furthermore, some of the circuits used within various functional unit blocks of a microprocessor may also employ current-mode logic CMOS. Consequently, it is desirable to interface single-ended signaling with differential signaling by providing a circuit that converts a single-ended signal into a differential signal.
A prior art single-ended to differential signal conversion circuit is illustrated in FIG. 2, where a single-ended voltage signal VIN is applied at input port 202 and a differential voltage signal represented by the voltages VOUT+ and VOUT− is taken at output ports 204 and 206, respectively. A reference voltage VREF is applied at port 208, which may nominally be (VCC–VSS)/2 where VCC is the supply voltage and VSS is substrate (ground) voltage.
Ideally, it would be desirable for the circuit of FIG. 2 to have wide common-mode performance, that is, for the circuit performance to be the same for VIN above VREF as for VIN below VREF. However, in practice, the performance is different for VIN in the range [VSS, (VCC–VSS)/2] than for the range [(VCC–VSS)/2, VCC]. For example, for VIN close to VSS, pFET Q3 may go out of its saturation region as its drain-to-source voltage becomes small, in which case it will not act like a high (small-signal) impedance load to nFET Q1, but for VIN in the range [(VCC–VSS)/2, VCC], pFET Q3 will present a high (small-signal) impedance load to nFET Q1, thereby resulting in a different amplifier gain for these two voltage regions.